The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of the IC evolution, functional density (defined as the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. A scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. But, such scaling down has increased the complexity of processing and manufacturing ICs. For these advances to be realized, similar developments in IC manufacturing are needed.
For example, as the semiconductor IC industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design have resulted in the development of three-dimensional (3D) vertical integration techniques. A wafer level stacking technique is one of the three-dimensional vertical integration techniques, which bonds two wafer structure by using bond structures. However, conventional bond structures and methods of fabricating the bond structures have not been entirely satisfactory in every aspect.